James Platt

I'm studying Electrical & Electronic Engineering at the University of Manchester and will be joining Alpine F1 in Electronics Design in July 2027.

Previously, I was the Electronics Lead for Manchester Stinger Motorsports, the university's Formula Student team, during the 2025–26 season.

My interests sit at the intersection of embedded systems, hardware design, low-level software (primarily C/C++), and more recently, FPGA development in VHDL and SystemVerilog.

Since school, I've built several things; from CAN nodes to mesh radio networks. I use this website to document a collection of both completed and ongoing projects, in a slightly less formal style than I've used before.

You can find more through my posts, or find me on GitHub, and LinkedIn.

Selected work